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TSL2571 light-to-digital converter taos117a ? february 2011 1 the lumenology company copyright 2011, taos inc. www.taosinc.com features ambient light sensing (als) ? approximates human eye response ? programmable analog gain ? programmable integration time ? programmable interrupt function with upper and lower threshold ? resolution up to 16 bits ? very high sensitivity ? operates well behind darkened glass ? up to 1,000,000:1 dynamic range programmable wait timer ? programmable from 2.72 ms to > 8 seconds ? wait state ? 65 a typical current i 2 c interface compatible ? up to 400 khz (i 2 c fast mode) ? dedicated interrupt pin small 2 mm 2 mm odfn package sleep mode ? 2.5 a typical current applications display management backlight control portable device power optimization cell phones, pda, gps notebooks and monitors lcd tvs description the TSL2571 family of devices provides ambient light sensing (als) that approximates human eye response to light intensity under a variety of lighting conditions and through a variety of attenuation materials. while useful for general purpose light sensing, the device is particularly useful for display management with the purpose of extending bat tery life and providing optimum viewing in diverse lighting conditions. display panel and keyboard backlighting can account for up to 30 to 40 percent of total platform power. the als features are ideal for use in notebook pcs, lcd monitors, flat-panel televisions, and cell phones. functional block diagram sda v dd int scl ch1 adc als control ch1 data wait control ch0 adc ch0 data ch0 ch1 upper limit lower limit interrupt i 2 c interface gnd texas advanced optoelectronic solutions inc. 1001 klein road suite 300 plano, tx 75074 (972) 673-0759 package fn dual flat no-lead (top view) v dd 1 scl 2 gnd 3 6 sda 5 int 4 nc ams ag technical content still valid
TSL2571 light-to-digital converter taos117a ? february 2011 2 copyright 2011, taos inc. the lumenology company www.taosinc.com detailed description the TSL2571 light-to-digital device includes on-chip photodiodes, integrating amplifiers, adcs, accumulators, clocks, buffers, comparators, a state machine, and an i 2 c interface. the device combines one photodiode (ch0), which is responsive to both visible and infrared light, and one photodiode (ch1), which is responsive primarily to infrared light. two integrating adcs simultaneously convert the amplified photodiode currents into a digital value providing up to 16 bits of resolution. upon completion of the conversion cycle, the conversion result is transferred to the data registers. this digital output can be read by a microprocessor through which the illuminance (ambient light level) in lux is derived using an empirical formula to approximate the human eye response. communication to the device is accomplished through a fast (up to 400 khz), two-wire i 2 c serial bus for easy connection to a microcontroller or embedded controller. the digital output of the device is inherently more immune to noise when compared to an analog interface. the device provides a separate pin for level-style interrupts. when interrupts are enabled and a pre-set value is exceeded, the interrupt pin is asserted and remains asserted until cleared by the controlling firmware. the interrupt feature simplifies and improves system efficiency by eliminating the need to poll a sensor for a light intensity value. an interrupt is generated when the value of an als conversion exceeds either an upper or lower threshold. in addition, a programmable interrupt persistence feature allows the user to determine how many consecutive exceeded thresholds are necessary to trigger an interrupt. interrupt thresholds and persistence settings are configured independently. ams ag technical content still valid
TSL2571 light-to-digital converter taos117a ? february 2011 3 the lumenology company copyright 2011, taos inc. www.taosinc.com terminal functions terminal type description name no. type description gnd 3 power supply ground. all voltages are referenced to gnd. int 5 o interrupt ? open drain (active low). nc 4 do not connect. scl 2 i i 2 c serial clock input terminal ? clock signal for i 2 c serial data. sda 6 i/o i 2 c serial data i/o terminal ? serial data i/o for i 2 c . v dd 1 supply voltage. available options device address package ? leads interface description ordering number TSL25711 0x39 fn?6 i 2 c vbus = v dd interface TSL25711fn TSL25713 0x39 fn?6 i 2 c vbus = 1.8 v interface TSL25713fn TSL25715 ? 0x29 fn?6 i 2 c vbus = v dd interface TSL25715fn TSL25717 ? 0x29 fn?6 i 2 c vbus = 1.8 v interface TSL25717fn ? contact taos for availability. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ? supply voltage, v dd (see note 1) 3.8 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital output voltage range, v o ?0.5 v to 3.8 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital output current, i o ?1 ma to 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ?40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . esd tolerance, human body model 2000 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditions? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: all voltages are with respect to gnd. recommended operating conditions min nom max unit supply voltage, v dd 2.6 3 3.6 v operating free-air temperature, t a ?30 70 c ams ag technical content still valid
TSL2571 light-to-digital converter taos117a ? february 2011 4 copyright 2011, taos inc. the lumenology company www.taosinc.com operating characteristics, v dd = 3 v, t a = 25 c (unless otherwise noted) parameter test conditions min typ max unit active 175 250 i dd supply current wait mode 65 a i dd supply current sleep mode ? no i 2 c activity 2.5 4 a v int sda output low voltage 3 ma sink current 0 0.4 v v ol int, sda output low voltage 6 ma sink current 0 0.6 v i leak leakage current, sda, scl, int pins ?5 5 a v scl sda input high voltage TSL25711, TSL25715 0.7 v dd v v ih scl, sda input high voltage TSL25713, TSL25717 1.25 v v scl sda input low voltage TSL25711, TSL25715 0.3 v dd v v il scl, sda input low voltage TSL25713, TSL25717 0.54 v als characteristics, v dd = 3 v, t a = 25 c, gain = 16, aen = 1 (unless otherwise noted) (notes 1 ,2, 3) parameter test conditions channel min typ max unit dark adc count value e e = 0, again = 120 , ch0 0 1 5 counts dark adc count value e e = 0 , again = 120 , atime = 0xdb (100 ms) ch1 0 1 5 counts adc integration time step size atime = 0xff 2.58 2.72 2.9 ms adc number of integration steps 1 256 steps adc counts per step atime = 0xff 0 1024 counts adc count value atime = 0xc0 0 65535 counts p = 625 nm, e e = 171.6 w/cm 2 , ch0 4000 5000 6000 adc count value p = 625 nm , e e = 171 . 6 w/cm , atime = 0xf6 (27 ms) see note 2. ch1 790 counts adc count value p = 850 nm, e e = 219.7 w/cm 2 , ch0 4000 5000 6000 counts p = 850 nm , e e = 219 . 7 w/cm , atime = 0xf6 (27 ms) see note 3. ch1 2800 625 nm atime 0xf6 (27 ms) see note 2 10 8 15 8 20 8 adc count value ratio: ch1/ch0 p = 625 nm, atime = 0xf6 (27 ms) see note 2. 10.8 15.8 20.8 % adc count value ratio: ch1/ch0 850 nm atime 0xf6 (27 ms) see note 3 41 56 68 % adc count value ratio: ch1/ch0 p = 850 nm, atime = 0xf6 (27 ms) see note 3. 41 56 68 % p = 625 nm, atime = 0xf6 (27 ms) ch0 29.1 r irradiance responsivity p = 625 nm , atime = 0xf6 (27 ms) see note 2. ch1 4.6 counts/ ( w/ r e irradiance responsivity p = 850 nm, atime = 0xf6 (27 ms) ch0 22.8 ( w/ c m 2 ) p = 850 nm , atime = 0xf6 (27 ms) see note 3. ch1 12.7 cm 2 ) gi li lti t 1 i 8 ?10 10 gain scalin g , relative to 1 g ain 16 10 10 % gain scaling , relative to 1 gain setting 16 ?10 10 % se tti ng 120 ?10 10 % notes: 1. optical measurements are made using small-angle incident radiation from light-emitting diode optical sources. visible 625 nm leds and infrared 850 nm leds are used for final product testing for compatibility with high-volume production. 2. the 625 nm irradiance e e is supplied by an al i ngap light-emitting diode with the following typical characteristics: peak wavelength p = 625 nm and spectral halfwidth ? ? = 20 nm. 3. the 850 nm irradiance e e is supplied by a gaas light-emitting diode with the following typical characteristics: peak wavelength p = 850 nm and spectral halfwidth ? ? = 42 nm. ams ag technical content still valid
TSL2571 light-to-digital converter taos117a ? february 2011 5 the lumenology company copyright 2011, taos inc. www.taosinc.com wait characteristics, v dd = 3 v, t a = 25 c, wen = 1 (unless otherwise noted) parameter test conditions channel min typ max unit wait step size wtime = 0xff 2.58 2.72 2.9 ms wait number of integration steps 1 256 steps ac electrical characteristics, v dd = 3 v, t a = 25 c (unless otherwise noted) parameter ? test conditions min typ max unit f (scl) clock frequency (i 2 c only) 0 400 khz t (buf) bus free time between start and stop condition 1.3 s t (hdsta) hold time after (repeated) start condition. after this period, the first clock is generated. 0.6 s t (susta) repeated start condition setup time 0.6 s t (susto) stop condition setup time 0.6 s t (hddat) data hold time 0 s t (sudat) data setup time 100 ns t (low) scl clock low period 1.3 s t (high) scl clock high period 0.6 s t f clock/data fall time 300 ns t r clock/data rise time 300 ns c i input pin capacitance 10 pf ? specified by design and characterization; not production tested. parameter measurement information sda scl stop start scl ack t (lowmext) t (lowmext) t (lowsext) scl ack t (lowmext) start condition stop condition p sda t (susto) t (sudat) t (hddat) t (buf) v ih v il scl t (susta) t (high) t (f) t (r) t (hdsta) t (low) v ih v il ps s figure 1. timing diagrams ams ag technical content still valid
TSL2571 light-to-digital converter taos117a ? february 2011 6 copyright 2011, taos inc. the lumenology company www.taosinc.com typical characteristics figure 2 spectral responsivity ? wavelength ? nm 0 400 0.2 0.4 0.6 0.8 1 500 600 700 800 900 1000 1100 normalized responsivity 300 ch 0 ch 1 figure 3 normalized i dd vs. v dd and temperature v dd ? v i dd normalized @ 3 v, 25 c 94% 96% 98% 100% 102% 104% 106% 108% 110% 92% 2.7 2.8 2.9 3 3.1 3.2 3.3 75 c 50 c 25 c 0 c figure 4 normalized responsivity vs. angular displacement ? angular displacement ? normalized responsivity 0 0.2 0.4 0.6 0.8 1.0 ?90 ?60 ?30 0 30 60 90 optical axis ams ag technical content still valid
TSL2571 light-to-digital converter taos117a ? february 2011 7 the lumenology company copyright 2011, taos inc. www.taosinc.com principles of operation system state machine the device provides control of als and power management functionality through an internal state machine (figure 5). after a power-on-reset, the device is in the sleep mode. as soon as the pon bit is set, the device will move to the start state. it will then continue through the wait and als states. if these states are enabled, the device will execute each function. if the pon bit is set to 0, the state machine will continue until all conversions are completed and then go into a low power sleep mode. sleep start wait als pon = 1 (r 0:b0) pon = 0 (r 0:b0) figure 5. simplified state diagram note: in this document, the nomenclature uses the bit field name in italic followed by the register number and bit number to allow the user to easily identify the register and bit that controls the function. for example, the power on (pon) is in register 0, bit 0. this is represented as pon (r0:b0). photodiodes conventional silicon detectors respond strongly to infrared light, which the human eye does not see. this can lead to significant error when the infrared content of the ambient light is high (such as with incandescent lighting) due to the difference between the silicon detector response and the brightness perceived by the human eye. this problem is overcome through the use of two photodiodes. the channel 0 photodiode, referred to as the ch0 channel, is sensitive to both visible and infrared light, while the channel 1 photodiode, referred to as ch1, is sensitive primarily to infrared light. two integrating adcs convert the photodiode currents to digital outputs. the adc digital outputs from the two channels are used in a formula to obtain a value that approximates the human eye response in units of lux. ams ag technical content still valid
TSL2571 light-to-digital converter taos117a ? february 2011 8 copyright 2011, taos inc. the lumenology company www.taosinc.com als operation the als engine contains als gain control (again) and two integrating analog-to-digital converters (adc) for the channel 0 and channel 1 photodiodes. the als integration time (atime) impacts both the resolution and the sensitivity of the als reading. integration of both channels occurs simultaneously and upon completion of the conversion cycle, the results are transferred to the data registers (c0data and c1data). this data is also referred to as channel count . the transfers are double-buffered to ensure data integrity. ch1 adc als control ch1 data ch0 als ch0 data again(r 0x0f, b1:0) 1 , 8 , 16 , 120 gain ch0 ch1 c0datah(r 0x15), c0data(r 0x14) c1datah(r 0x17), c1data(r 0x16) atime(r 1) 2.72 ms to 696 ms figure 6. als operation the registers for programming the integration and wait times are a 2?s compliment values. the actual time can be calculated as follows: atime = 256 ? integration time / 2.72 ms inversely, the time can be calculated from the register value as follows: integration time = 2.72 ms (256 ? atime) in order to reject 50/60-hz ripple strongly present in fluorescent lighting, the integration time needs to be programmed in multiples of 10 / 8.3 ms or the half cycle time. both frequencies can be rejected with a programmed value of 50 ms (atime = 0xed) or multiples of 50 ms (i.e. 100, 150, 200, 400, 600). the registers for programming the again hold a two-bit value representing a gain of 1 , 8 , 16 , or 120 . the gain, in terms of amount of gain, will be represented by the value againx, i.e. againx = 1, 8, 16, or 120. lux equation the lux calculation is a function of ch0 channel count (c0data), ch1 channel count (c1data), als gain (againx), and als integration time in milliseconds (atime_ms). if an aperture, glass/plastic, or a light pipe attenuates the light equally across the spectrum (300 nm to 1100 nm), then a scaling factor referred to as glass attenuation (ga) can be used to compensate for attenuation. for a device in open air with no aperture or glass/plastic above the device, ga = 1. if it is not spectrally flat, then a custom lux equation with new coef ficients should be generated. (see taos application note). counts per lux (cpl) needs to be calculated only when atime or again is changed, otherwise it remains a constant. the first segment of the equation (lux1) covers fluorescent and incandescent light. the second segment (lux2) covers dimmed incandescent light. the final lux is the maximum of lux1, lux2, or 0. cpl = (atime_ms againx) / (ga 53) lux1 = (c0data ? 2 c1data) / cpl lux2 = (0.6 c0data ? c1data) / cpl lux = max(lux1, lux2, 0) ams ag technical content still valid
TSL2571 light-to-digital converter taos117a ? february 2011 9 the lumenology company copyright 2011, taos inc. www.taosinc.com interrupts the interrupt feature simplifies and improves system efficiency by eliminating the need to poll the sensor for light intensity values outside of a user-defined range. while the interrupt function is always enabled and it?s status is available in the status register (0x13), the output of the interrupt state can be enabled using the als interrupt enable (aien) field in the enable register (0x00). two 16-bit interrupt threshold registers allow the user to set limits below and above a desired light level range. an interrupt can be generated when the als ch0 data (c0data) falls outside of the desired light level range, as determined by the values in the als interrupt low threshold registers (ailtx) and als interrupt high threshold registers (aihtx). it is important to note that the low threshold value must be less than the high threshold value for proper operation. to further control when an interrupt occurs, the device provides a persistence filter. the persistence filter allows the user to specify the number of consecutive out-of-range als occurrences before an interrupt is generated. the persistence register (0x0c) allows the user to set the als persistence (apers) value. see the persistence register for details on the persistence filter values. once the persistence filter generates an interrupt, it will continue until a special function interrupt clear command is received (see command register). ch0 adc ch0 data ch0 upper limit lower limit aihth(r 07), aihtl(r 06) als persistence ailth(r 05), ailtl(r 04) apers(r 0x0c, b3:0) figure 7. programmable interrupt ams ag technical content still valid
TSL2571 light-to-digital converter taos117a ? february 2011 10 copyright 2011, taos inc. the lumenology company www.taosinc.com state diagram figure 8 shows a more detailed flow for the state machine. the device starts in the sleep mode. the pon bit is written to enable the device. a 2.72-ms delay will occur before entering the start state. if the wen bit is set, the state machine will then cycle through the wait state. if the wlong bit is set, the wait cycles are extended by 12 over normal operation. when the wait counter terminates, the state machine will step to the als state. the aen should always be set. in this case, a minimum of 1 integration time step should be programmed. the als state machine will continue until it reaches the terminal count at which point the data will be latched in the als register and the interrupt set, if enabled. pon = 1 pon = 0 sleep als check wait check start wait wen = 1 als 1 to 256 steps step: 2.72 ms time: 2.72 ms ? 696 ms 120 hz minimum ? 8 ms 100 hz minimum ? 10 ms wlong = 0 1 to 256 steps step: 2.72 ms time: 2.72 ms ? 696 ms minimum ? 2.72 ms wlong = 1 1 to 256 steps step: 32.64 ms time: 32.64 ms ? 8.35 s minimum ? 32.64 ms als delay aen = 1 2.72 ms figure 8. expanded state diagram ams ag technical content still valid
TSL2571 light-to-digital converter taos117a ? february 2011 11 the lumenology company copyright 2011, taos inc. www.taosinc.com i 2 c protocol interface and control are accomplished through an i 2 c serial compatible interface (standard or fast mode) to a set of registers that provide access to device control functions and output data. the devices support the 7-bit i 2 c addressing protocol. the i 2 c standard provides for three types of bus transaction: read, write, and a combined protocol (figure 17). during a write operation, the first byte written is a command byte followed by data. in a combined protocol, the first byte written is the command byte followed by reading a series of bytes. if a read command is issued, the register address from the previous command will be used for data access. likewise, if the msb of the command is not set, the device will write a series of bytes at the address stored in the last valid command with a register address. the command byte contains either control information or a 5-bit register address. the control commands can also be used to clear interrupts. the i 2 c bus protocol was developed by philips (now nxp). for a complete description of the i 2 c protocol, please review the nxp i 2 c design specification at http ://www.i2c?bus.org/references/. a acknowledge (0) n not acknowledged (1) p stop condition r read (1) s start condition s repeated start condition w write (0) ... continuation of protocol master-to-slave slave-to-master w 7 data byte slave address s 1 aa a 8 11 1 8 command code 1 p 1 ... i 2 c write protocol i 2 c read protocol i 2 c read protocol ? combined format r 7 data slave address s 1 aa a 8 11 1 8 data 1 p 1 ... w 7 slave address slave address s 1 ar a 8 11 1 7 11 command code s 1 a data a a 81 8 data 1 p 1 ... figure 9. i 2 c protocols ams ag technical content still valid
TSL2571 light-to-digital converter taos117a ? february 2011 12 copyright 2011, taos inc. the lumenology company www.taosinc.com register set the device is controlled and monitored by data registers and a command register accessed through the serial interface. these registers provide for a variety of control functions and can be read to determine results of the adc conversions. the register set is summarized in table 1. table 1. register address address resister name r/w register function reset value ?? command w specifies register address 0x00 0x00 enable r/w enables states and interrupts 0x00 0x01 atime r/w als adc time 0xff 0x03 wtime r/w wait time 0xff 0x04 ailtl r/w als interrupt low threshold low byte 0x00 0x05 ailth r/w als interrupt low threshold high byte 0x00 0x06 aihtl r/w als interrupt high threshold low byte 0x00 0x07 aihth r/w als interrupt high threshold high byte 0x00 0x0c pers r/w interrupt persistence filters 0x00 0x0d config r/w configuration 0x00 0x0f control r/w control register 0x00 0x12 id r device id id 0x13 status r device status 0x00 0x14 c0data r ch0 adc low data register 0x00 0x15 c0datah r ch0 adc high data register 0x00 0x16 c1data r ch1 adc low data register 0x00 0x17 c1datah r ch1 adc high data register 0x00 the mechanics of accessing a specific register depends on the specific protocol used. see the section on i 2 c protocols on the previous pages. in general, the command register is written first to specify the specific control/status register for following read/write operations. ams ag technical content still valid
TSL2571 light-to-digital converter taos117a ? february 2011 13 the lumenology company copyright 2011, taos inc. www.taosinc.com command register the command registers specifies the address of the target register for future write and read operations. table 2. command register 6 754 add 2 310 command command type ? ? field bits description command 7 select command register. must write as 1 when addressing command register. type 6:5 selects type of transaction to follow in subsequent data transfers: field value description 00 repeated byte protocol transaction 01 auto-increment protocol transaction 10 reserved ? do not use 11 special function ? see description below transaction type 00 will repeatedly read the same register with each data access. transaction type 01 will provide an auto-increment function to read successive register bytes. add 4:0 address register/special function field. depending on the transaction type, see above, this field either specifies a special function command or selects the specific control-status-register for following write and read transactions. the field values listed below apply only to special function commands: field value description 00000 normal ? no action 00110 als interrupt clear other reserved ? do not write als interrupt clear ? clears any pending als interrupt. this special function is self clearing. ams ag technical content still valid
TSL2571 light-to-digital converter taos117a ? february 2011 14 copyright 2011, taos inc. the lumenology company www.taosinc.com enable register (0x00) the enable register is used to power the device on/off, enable functions, and interrupts. table 3. enable register 6 754 pon 2 310 enable reserved aien address 0x00 aen wen reserved field bits description reserved 7:5 reserved. write as 0. aien 4 als interrupt mask. when asserted, permits als interrupts to be generated. wen 3 wait enable. this bit activates the wait feature. writing a 1 activates the wait timer. writing a 0 disables the wait timer. reserved 2 reserved. write as 0. aen 1 als enable. writing a 1 activates the als. writing a 0 disables the als. pon 1 0 power on. this bit activates the internal oscillator to permit the timers and adc channels to operate. writing a 1 activates the oscillator. writing a 0 disables the oscillator. note 1: a minimum interval of 2.72 ms must pass after pon is asserted before als can be initiated. this required time is enforc ed by the hardware in cases where the firmware does not provide it. als timing register (0x01) the als timing register controls the internal integration time of the als adcs in 2.72-ms increments. table 4. als timing register field bits description atime 7:0 value integ_cycles time max count 0xff 1 2.72 ms 1024 0xf6 10 27.2 ms 10240 0xdb 37 101 ms 37888 0xc0 64 174 ms 65535 0x00 256 696 ms 65535 ams ag technical content still valid
TSL2571 light-to-digital converter taos117a ? february 2011 15 the lumenology company copyright 2011, taos inc. www.taosinc.com wait time register (0x03) wait time is set 2.72 ms increments unless the wlong bit is asserted in which case the wait times are 12 longer. wtime is programmed as a 2?s complement number. table 5. wait time register field bits description wtime 7:0 register value wait time time (wlong = 0) time (wlong = 1) 0xff 1 2.72 ms 0.032 sec 0xb6 74 201 ms 2.4 sec 0x00 256 696 ms 8.3 sec note: the wait time register should be configured before aen is asserted. als interrupt threshold registers (0x04 ? 0x07) the als interrupt threshold registers provides the values to be used as the high and low trigger points for the comparison function for interrupt generation. if c0data crosses below the low threshold specified, or above the higher threshold, an interrupt is asserted on the interrupt pin. table 6. als interrupt threshold registers register address bits description ailtl 0x04 7:0 als low threshold lower byte ailth 0x05 7:0 als low threshold upper byte aihtl 0x06 7:0 als high threshold lower byte aihth 0x07 7:0 als high threshold upper byte ams ag technical content still valid
TSL2571 light-to-digital converter taos117a ? february 2011 16 copyright 2011, taos inc. the lumenology company www.taosinc.com persistence register (0x0c) the persistence register controls the filtering interrupt capabilities of the device. configurable filtering is provided to allow interrupts to be generated after each adc integration cycle or if the adc integration has produced a result that is outside of the values specified by threshold register for some specified amount of time. als interrupts are generated using c0data. table 7. persistence register 6 754 apers 2 310 pers reserved address 0x0c field bits description reserved 7:4 reserved apers 3:0 interrupt persistence. controls rate of interrupt to the host processor. field value meaning interrupt persistence function 0000 every every als cycle generates an interrupt 0001 1 1 value outside of threshold range 0010 2 2 consecutive values out of range 0011 3 3 consecutive values out of range 0100 5 5 consecutive values out of range 0101 10 10 consecutive values out of range 0110 15 15 consecutive values out of range 0111 20 20 consecutive values out of range 1000 25 25 consecutive values out of range 1001 30 30 consecutive values out of range 1010 35 35 consecutive values out of range 1011 40 40 consecutive values out of range 1100 45 45 consecutive values out of range 1101 50 50 consecutive values out of range 1110 55 55 consecutive values out of range 1111 60 60 consecutive values out of range configuration register (0x0d) the configuration register sets the wait long time. table 8. configuration register 6 7542 310 config reserved wlong address 0x0d reserved field bits description reserved 7:2 reserved. write as 0. wlong 1 wait long. when asserted, the wait cycles are increased by a factor 12 from that programmed in the wtime register. reserved 0 reserved. write as 0. ams ag technical content still valid
TSL2571 light-to-digital converter taos117a ? february 2011 17 the lumenology company copyright 2011, taos inc. www.taosinc.com control register (0x0f) the control register provides eight bits of miscellaneous control to the analog block. these bits typically control functions such as gain settings and/or diode selection. table 9. control register 6 7542 310 control reserved address 0x0f again field bits description reserved 7:2 reserved. write bits as 0 again 1:0 als gain control. field value als gain value 00 1 gain 01 8 gain 10 16 gain 11 120 gain id register (0x12) the id register provides the value for the part number. the id register is a read-only register. table 10. id register 6 7542 310 id id address 0x12 field bits description id 7:0 part number identification 0x04 = TSL25711 & TSL25715 id 7:0 part number identification 0x0d = TSL25713 & TSL25717 status register (0x13) the status register provides the internal status of the device. this register is read only. table 11. status register 6 754 avalid 2 310 status reserved aint address 0x13 reserved field bit description reserved 7:5 reserved. write as 0. aint 4 als interrupt. indicates that the device is asserting an als interrupt. reserved 3:1 reserved. avalid 0 als valid. indicates that the als ch0 / ch1 channels have completed an integration cycle. ams ag technical content still valid
TSL2571 light-to-digital converter taos117a ? february 2011 18 copyright 2011, taos inc. the lumenology company www.taosinc.com adc channel data registers (0x14 ? 0x17) als data is stored as two 16?bit values. to ensure the data is read correctly, a two?byte read i2c transaction should be used with auto increment protocol bits set in the command register. with this operation, when the lower byte register is read, the upper eight bits are stored in a shadow register, which is read by a subsequent read to the upper byte. the upper register will read the correct value even if additional adc integration cycles end between the reading of the lower and upper registers. table 12. adc channel data registers register address bits description c0data 0x14 7:0 als ch0 data low byte c0datah 0x15 7:0 als ch0 data high byte c1data 0x16 7:0 als ch1 data low byte c1datah 0x17 7:0 als ch1 data high byte ams ag technical content still valid
TSL2571 light-to-digital converter taos117a ? february 2011 19 the lumenology company copyright 2011, taos inc. www.taosinc.com application information: hardware typical hardware application a typical hardware application circuit is shown in figure 10. a 1- f low-esr decoupling capacitor should be placed as close as possible to the v dd pin. TSL2571 int sda scl v dd 1 f gnd v bus r p r p r pi v dd figure 10. typical application hardware circuit v bus in figure 10 refers to the i 2 c bus voltage, which is either v dd or 1.8 v. be sure to apply the specified i 2 c bus voltage shown in the available options table for the specific device being used. the i 2 c signals and the interrupt are open-drain outputs and require pull-up resistors. the pull-up resistor (r p ) value is a function of the i 2 c bus speed, the i 2 c bus voltage, and the capacitive load. the taos evm running at 400 kbps, uses 1.5-k resistors. a 10-k pull-up resistor (r pi ) can be used for the interrupt line. pcb pad layout suggested pcb pad layout guidelines for the dual flat no-lead (fn) surface mount package are shown in figure 11. 400 2500 400 1000 1700 650 1000 650 note: pads can be extended further if hand soldering is needed. notes: a. all linear dimensions are in micrometers. b. this drawing is subject to change without notice. figure 11. suggested fn package pcb layout ams ag technical content still valid
TSL2571 light-to-digital converter taos117a ? february 2011 20 copyright 2011, taos inc. the lumenology company www.taosinc.com mechanical data package fn dual flat no-lead 203 8 6 sda 5 int 4 nc v dd 1 scl 2 gnd 3 top view side view bottom view lead free pb 300 50 650 2000 100 2000 100 pin 1 pin 1 end view 650 50 pin out top view 750 150 photodiode array area 295 nominal 466 10 466 10 c l of solder contacts c l of photodiode array area (note b) 20 nominal c l of solder contacts of photodiode array area (note b) c l 140 nominal notes: a. all linear dimensions are in micrometers. dimension tolerance is 20 m unless otherwise noted. b. the die is centered within the package within a tolerance of 3 mils. c. package top surface is molded with an electrically nonconductive clear plastic compound having an index of refraction of 1.55 . d. contact finish is copper alloy a194 with pre-plated nipdau lead finish. e. this package contains no lead (pb). f. this drawing is subject to change without notice. figure 12. package fn ? dual flat no-lead packaging configuration ams ag technical content still valid
TSL2571 light-to-digital converter taos117a ? february 2011 21 the lumenology company copyright 2011, taos inc. www.taosinc.com mechanical data top view detail a 2.18 0.05 a o 0.254 0.02 5 max 4.00 8.00 3.50 0.05 1.50 4.00 2.00 0.05 + 0.30 ? 0.10 1.75 b b aa 1.00 0.25 detail b 2.18 0.05 b o 5 max 0.83 0.05 k o notes: a. all linear dimensions are in millimeters. dimension tolerance is 0.10 mm unless otherwise noted. b. the dimensions on this drawing are for illustrative purposes only. dimensions of an actual carrier may vary slightly. c. symbols on drawing a o , b o , and k o are defined in ansi eia standard 481?b 2001. d. each reel is 178 millimeters in diameter and contains 3500 parts. e. taos packaging tape and reel conform to the requirements of eia standard 481?b. f. in accordance with eia standard, device pin 1 is located next to the sprocket holes in the tape. g. this drawing is subject to change without notice. figure 13. package fn carrier tape ams ag technical content still valid
TSL2571 light-to-digital converter taos117a ? february 2011 22 copyright 2011, taos inc. the lumenology company www.taosinc.com manufacturing information the fn package has been tested and has demonstrated an ability to be reflow soldered to a pcb substrate. the solder reflow profile describes the expected maximum heat exposure of components during the solder reflow process of pr oduct on a pcb. temperature is measured on top of component. the components should be limited to a maximum of three passes through this solder reflow profile. table 13. solder reflow profile parameter reference device average temperature gradient in preheating 2.5 c/sec soak time t soak 2 to 3 minutes time above 217 c (t1) t 1 max 60 sec time above 230 c (t2) t 2 max 50 sec time above t peak ?10 c (t3) t 3 max 10 sec peak temperature in reflow t peak 260 c temperature gradient in cooling max ?5 c/sec t 3 t 2 t 1 t soak t 3 t 2 t 1 t peak not to scale ? for reference only time (sec) temperature ( c) figure 14. solder reflow profile graph ams ag technical content still valid
TSL2571 light-to-digital converter taos117a ? february 2011 23 the lumenology company copyright 2011, taos inc. www.taosinc.com manufacturing information moisture sensitivity optical characteristics of the device can be adversely affected during the soldering process by the release and vaporization of moisture that has been previously absorbed into the package. to ensure the package contains the smallest amount of absorbed moisture possible, each device is dry-baked prior to being packed for shipping. devices are packed in a sealed aluminized envelope called a moisture barrier bag with silica gel to protect them from ambient moisture during shipping, handling, and storage before use. the fn package has been assigned a moisture sensitivity level of msl 3 and the devices should be stored under the following conditions: temperature range 5 c to 50 c relative humidity 60% maximum total time 12 months from the date code on the aluminized envelope ? if unopened opened time 168 hours or fewer rebaking w ill be required if the devices have been stored unopened for more than 12 months or if the aluminized envelope has been open for more than 168 hours. if rebaking is required, it should be done at 50 c for 12 hours. ams ag technical content still valid
TSL2571 light-to-digital converter taos117a ? february 2011 24 copyright 2011, taos inc. the lumenology company www.taosinc.com production data ? information in this document is current at publication date. products conform to specifications in accordance with the terms of texas advanced optoelectronic solutions, inc. standard warranty. production processing does not necessarily include testing of all parameters. lead-free (pb-free) and green statement pb-free (rohs) taos? terms lead-free or pb-free mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, taos pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br) taos defines green to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material). important information and disclaimer the information provided in this statement represents taos? knowledge and belief as of the date that it is provided. taos bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. taos has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. taos and taos suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. notice texas advanced optoelectronic solutions, inc. (t aos) reserves the right to make changes to the products contained in this document to improve performance or for any other purpose, or to discontinue them without notice. customers are advised to contact taos to obtain the latest product information before placing orders or designing taos products into systems. taos assumes no responsibility for the use of any products or circuits described in this document or customer product design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that the circuits are free of patent infringement. taos further makes no claim as to the suitability of its products for any particu lar purpose, nor does taos assume any liability arising out of the use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. texas advanced optoelectronic solutions, inc. products are not designed or intended for use in critical applications in which the failure or malfunction of the taos product may result in personal injury or death. use of t aos products in life support systems is expressly unauthorized and any such use by a customer is completely at the customer?s risk. lumenology, taos, the taos logo, and texas advanced optoelectronic solutions are registered trademarks of texas advanced optoelectronic solutions incorporated. ams ag technical content still valid

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